Integrated circuits that include MOS transistors are particularly susceptible to damage by electrostatic discharge (ESD) events, e.g. when the circuit is touched by a person handling the circuit causing static electricity to discharge from the handler through the circuit. This is particularly the case once the circuit has been packaged but prior to it being installed in a product.
Different protection circuits have been developed to deal with ESD events, one of these involving the use of BJT or MOS transistors or SCR devices that shunt ESD current to ground. In order to control the turn-on of the shunt, the gate electrode of the shunt may be controlled. This may involve biasing the gate electrode using a forward biased diode or a reverse biased Zener diode. One such prior art control circuit is shown in FIG. 1, which includes a diode 100 controlling the gate of a BJT 102. In the case of an ESD event to the VDD rail, a voltage peak is produced over the diode 100 and resistor 104. When the diode 100 turns on (at about 1 V over the diode) it provides a bias voltage to the gate of the BJT 102 as defined by the voltage over the resistor 104. The BJT 102 in this case acts as a shunt operating in snapback mode or in normal mode to shunt current from the pad 104 to ground in the event of an ESD event. Another prior art device is shown in FIG. 2, which shows a Zener diode 200 controlling an NMOS device 202. A typical reverse biased Zener diode such as Zener 202 will turn on at about 15V, thus the Zener 202 will provide a gate bias voltage to the NMOS device as dictated by the voltage over the resistor 204.
Instead of using a control or trigger circuit such as the diode 100 or zener diode 200 to provide the gate bias voltage by means of a resistor, another prior art approach involves the use of a resistor-capacitor (RC) circuit. One such circuit is shown in FIG. 3. This circuit comprises an RC circuit as defined by a capacitor 300 and a resistor 302. The RC circuit controls the triggering of an NMOS device 304 as is discussed in greater detail below. During normal operation, the junction breakdown of the NMOS snapback device 304 is greater than VDD. Thus VDD will simply charge up the capacitor 300 and hold the node 306 at VDD. The node voltage is inverted by the inverter 310 which applies the resultant low voltage to the substrate and gate of the NMOS 304, thereby ensuring that the junction breakdown of the NMOS is not affected and the NMOS does not trigger. The time constant of the RC circuit is typically chosen to be about 1 to 10 μs. In contrast, the impulse at power on has a duration of the order of milliseconds. Thus, the much shorter time constant of the RC circuit allows zero volts to be is applied to the substrate and gate of the NMOS 304 virtually instantaneously, causing little leakage. An ESD event across the power line VDD and ground, on the other hand, has a much shorter duration than the RC time constant, being of the order of several nanoseconds. Thus the capacitor 300 will not be able to respond in time to the large ESD voltage peak. This causes the node 306 to be substantially grounded, causing an increased gate driving voltage and substrate triggering voltage. This reduces the breakdown voltage of the NMOS 304 and causes it to go into snapback mode, thereby shunting ESD current to ground. The problem with this configuration is that as CMOS processes continue to advance, e.g., 90 nm geometry, the gate oxide becomes increasingly leaky, therefore any capacitors that include a gate oxide will leak under normal operation. In fact the leakage current through a capacitor that includes a gate oxide can be as much as the current through the resistor. Thus it is difficult to realize a good RC time constant for an RC trigger circuit. The present invention seeks to address this issue.